Semiconductor memory device

ABSTRACT

A semiconductor memory device comprising a pair of bit lines, a word line, a cell plate electrode, a memory cell connected to each of the bit lines, the word line and the cell plate electrode, and a prevention means that permits only a predetermined number of readouts of data stored in the memory cell, after which the data is destroyed and is not retrieved with subsequent readout attempts.

BACKGROUND OF THE INVENTION

Dynamic Random Access Memory chips (DRAMs) are widely used amongsemiconductor memory devices because of their high density and low cost.The basic operation of a DRAM is to record data by storing bits as thepresence ("1") or absence ("0") of electrical charge in memory cellcapacitors. Silicon oxide is traditionally used as the dielectric layerof the memory cell capacitor of the DRAM, but recently DRAMS have beendeveloped using a ferroelectric layer instead.

A circuit diagram of a semiconductor memory device using ferroelectriccapacitors as taught by prior art is represented in FIG. 27. FIG. 27depicts a semiconductor memory device having four memory cells 30a, 30b,30c, 30d arranged in two rows and two columns, although a differentnumber of memory cells could be provided. In any case, each memory cellis similarly structured, so the operation of the semiconductor memorydevice may be explained with respect to memory cell 30a with theunderstanding that corresponding operations can be applied to the othermemory cells as well.

In memory cell 30a, one of a pair of ferroelectric capacitors 33a isconnected through one of a pair of MOS transistors 31a to bit line 35;the other ferroelectric capacitor 33a is connected through the other MOStransistor 31a to bit line 36. The gates of both MOS transistors 31a arecontrolled by word line 32, and both ferroelectric capacitors 33a areconnected to cell plate electrode 39. Signal line 47 supplies controlsignal φP to MOS transistors 43, 44, either grounding or precharging bitlines 35, 36. A second signal line 49 supplies control signal φS tosense amplifier 41.

In a memory cell such as 30a, comprised of two ferroelectric capacitors33a and two MOS transistors 31a, data is written by applying logicalvoltages of opposite polarities to the pair of ferroelectric capacitors33a. The stored data can then be read by reading out the residualcharges from the pair of ferroelectric capacitors 33a onto the pair ofbit lines 35, 36, and amplifying the potential difference between thebit lines 35, 36 with the sense amplifier 41.

The operation of the prior art semiconductor memory device of FIG. 27can be explained in greater detail with reference to FIGS. 28 and 29.FIG. 28 shows a hysteresis curve; FIG. 29 is a timing chart of a readoutoperation on memory cell 30a.

As shown in FIG. 28, initially, word line 32, cell plate electrode 39,bit lines 35, 36 and signal line 49 supplying control signal φS are allat a low logical voltage "L". While signal line 47 supplying controlsignal φP is at a high logical voltage "H". To enable the memory deviceto read the data stored in ferroelectric capacitors 33a, signal line 47is changed to "L", shifting bit lines 35, 36 to a floating state. Wordline 32 and cell plate electrode 39 are then changed to "H", turning onMOS transistors 31a and enabling the data stored in ferroelectriccapacitors 33a to be read out onto bit lines 35, 36.

The potential difference between the charges read out from ferroelectriccapacitors 33a onto bit lines 35, 36 is shown in the hysteresis curve ofFIG. 28. After data is stored in a ferroelectric capacitor and the powersupply is cut off, the electric field is zero and the residual chargesin the ferroelectric capacitor are utilized as nonvolatile data. Theresidual charge for high and low voltages are represented respectivelyby points B and E: When the data value stored in a memory cell is a "1",a first of the pair of ferroelectric capacitors stands at point B andthe other stands at point E. When the data value stored in a memory cellis a "0", the situation is reversed, with the first ferroelectriccapacitor at point E and the other at point B.

Still referring to FIG. 28, the slopes of straight lines L1, L2 dependon the parasitic capacitance of bit lines 35, 36: the less parasitic thecapacitance, the smaller the absolute value of the slope. Points M21 andN21 are found by horizontally shifting points B and E by a magnitude ofelectric field produced when the voltages of word line 32 and cell plateelectrode 39 are at a logical voltage "H".

The curves from the points B and E to point D represent the electricalcharge held in ferroelectric capacitors 33a as the electrical fieldchanges due to the voltage shift of word line 32 and cell plateelectrode 39 from "L" to "H". When a stored data value "1" is read outonto bit line 35 from a first of the pair of ferroelectric capacitors33a, the state of that ferroelectric capacitor 33a moves from point B topoint 021, where the hysteresis curve intersects with line L1.Similarly, the state of the second ferroelectric capacitor 33a, whichcarries an opposite logical value from the first ferroelectric capacitor33a, moves from point E to point P21, where the hysteresis curveintersects with line L2. Thus the read-out potential difference betweenthe pair of bit lines 35, 36 becomes Vr21, the difference between theelectric fields at point 021 and point P21.

To read the data on bit lines 35, 36, the potential difference Vr21 isamplified and signal line 49 supplying control signal φS is shifted from"L" to "H". When the amplification in the sense amplifier 41 iscomplete, the state of bit line 35 shifts from point 021 to point Q21,and the state of bit line 36 shifts from point P21 to point D.

When the data is read, the charges in ferroelectric capacitors 33adissipate and must be rewritten. Voltage at cell plate electrode 39shifts from "L" to "H", moving bit line 35 from point Q21 to point A.Similarly, bit line 36 moves from point D to point E. This completes therewriting process, and the semiconductor memory device is now restoredto its initial state: word line 32 and control signal φS are shifted to"L", signal line 47 is shifted to "H", and bit lines 35, 36 are returnedto "L" from floating state.

If the value stored in memory cell 30a is "0" rather than "1", with theeffect that the first of the pair of ferroelectric capacitors 33a storesa "0" and the other ferroelectric capacitor 33a stores a "1", the statesof the bit lines 35, 36 are reversed, but the process remains the sameand the potential difference remains Vr21.

The prior art semiconductor memory device described above is able towrite data into its memory, as well as read and rewrite stored data frommemory. However, having no means to monitor the number of readoutsperformed, it is impossible to limit data readout operations to a numberagreed upon between the data offerer and the data user.

Moreover, a semiconductor memory device as taught by the prior art hasno security feature to prevent an outsider from reading normal datastored in it. Thus, if a user fails to erase information stored asnormal data in the device after completing use of that information, anoutsider who obtains the device can read out that information as normaldata.

Accordingly, there exists a need for a semiconductor memory device withthe enhanced capability to limit the number of data readouts to apredetermined maximum limit, as well as to provide a security feature toautomatically change information stored as normal data to abnormal dataafter the information is no longer needed by the user, in order toprevent outsiders from being able to read out information stored on thedevice as normal data.

SUMMARY OF THE INVENTION

The present invention provides such a semiconductor memory devicecapable of limiting the number of normal data readouts.

Accordingly, the present invention relates to a semiconductor memorydevice comprising a pair of bit lines, a word line, a cell plateelectrode, a memory cell for storing data, connected to the pair of bitlines, the word line and the cell plate electrode, and prevention meansfor preventing normal readout of the stored data, after the number ofreadouts executed on the stored data reaches a predetermined limitingnumber of readouts permitted.

The present invention also relates to a method of limiting the number ofnormal readouts of data stored in a semiconductor memory device bydetermining whether the number of readouts already executed on thestored data has reached the predetermined limiting number of readoutspermitted, and accordingly, preventing subsequent readouts if thepredetermined limiting number has been reached.

As described in detail below, the semiconductor memory device of thepresent invention may limit the number of data readout operations in avariety of ways. Illustrative means include causing erratic readout ofthe data, destroying stored data, inhibiting the writing of normal data,and inhibiting the rewriting of read out data.

The invention itself, together with further objects and attendantadvantages, will be understood by reference to the following detaileddescription, taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic circuit diagram of the present invention in afirst embodiment.

FIG. 2 shows a timing chart of a readout operation of the presentinvention in a first embodiment.

FIG. 3 is a hysteresis curve of a ferroelectric capacitor of the presentinvention in a first embodiment.

FIG. 4 shows a schematic circuit diagram of the present invention in asecond embodiment.

FIG. 5 shows a timing chart of a readout operation of the presentinvention in a second embodiment.

FIG. 6 is a hysteresis curve of a ferroelectric capacitor of the presentinvention in a second embodiment.

FIG. 7 shows a schematic circuit diagram of the present invention in athird and a fourth embodiment.

FIG. 8 shows a hysteresis curve of a ferroelectric capacitor of thepresent invention in a third embodiment.

FIG. 9 shows a hysteresis curve of a ferroelectric capacitor of thepresent invention in a fourth embodiment.

FIG. 10 shows a schematic circuit diagram of the present invention in afifth, an eighth and a ninth embodiment.

FIG. 11 shows a timing chart of a readout operation of the presentinvention in a fifth embodiment.

FIG. 12 shows a hysteresis curve of a ferroelectric capacitor of thepresent invention in a fifth embodiment.

FIG. 13 shows a schematic circuit diagram of the present invention in asixth embodiment.

FIG. 14 shows a timing chart of a readout operation of the presentinvention in a sixth embodiment.

FIG. 15 shows a hysteresis curve of a ferroelectric capacitor of thepresent invention in a sixth embodiment.

FIG. 16 shows a timing chart of a variation of a readout operation ofthe present invention in the sixth embodiment.

FIG. 17 shows a hysteresis characteristics of the ferroelectriccapacitor of the present invention in a variation of the sixthembodiment.

FIG. 18 shows a schematic circuit diagram of the present invention in aseventh embodiment.

FIG. 19 shows a timing chart of the readout operation of the presentinvention in a seventh embodiment.

FIG. 20 shows a hysteresis curve of a ferroelectric capacitor of thepresent invention in a seventh embodiment.

FIG. 21 shows a timing chart of a readout operation of the presentinvention in an eighth embodiment.

FIG. 22 shows a hysteresis curve of a ferroelectric capacitor of thepresent invention in an eighth embodiment.

FIG. 23 shows a timing chart of a readout operation of the presentinvention in a ninth embodiment.

FIG. 24 shows a hysteresis curve of a ferroelectric capacitor of thepresent invention in a ninth embodiment.

FIG. 25 shows a schematic circuit diagram of the present invention in atenth embodiment.

FIG. 26 shows a schematic circuit diagram of the present invention in aneleventh embodiment.

FIG. 27 shows a schematic circuit diagram of a conventionalsemiconductor memory device as taught by prior art.

FIG. 28 shows a hysteresis curve of a ferroelectric capacitor used in aconventional semiconductor memory device as taught by prior art.

FIG. 29 shows a timing chart of a readout operation of a conventionalsemiconductor memory device as taught by prior art.

DETAILED DESCRIPTION OF THE DRAWINGS

Turning now to the drawings, the schematic circuit diagram of FIG. 1illustrates the components of the present invention in a firstembodiment. As shown, a semiconductor memory device as taught by thisinvention is comprised of MOS transistors Qn00, Qn00B, Qn01, Qn01B,Qn10, Qn10B, Qn11, QN11B, ferroelectric capacitors Cs00, Cs00B, Cs01,Cs01B, Cs10, Cs10B, Cs11, Cs11B, word lines WL0, WL1, bit lines BL0,/BL0, BL1, /BL1, cell plate electrodes CP0, CP1, sense amplifiers SA0,SA1, signal lines LCBC, LVcc, LEQ, LVss, LSAE, limiting capacitors Ct0,Ct1 for limiting the number of readout operations, adjusting capacitorsCb00, Cb00B, Cb10, Cb10B for adjusting the bit line capacitance,limiting MOS transistors Qnt0, Qnt1 for limiting the number of readoutoperations, controlling MOS transistors Qne0, Qne1, Qne2, Qne2B, Qne3,Qne3B for controlling the signals, judging circuit 3 for comparing thedata, nonvolatile memory device 4 for setting a limiting number ofreadouts, and subtraction circuit 5 for keeping a record of the numberof readouts already performed.

Each memory cell in this first embodiment of the present invention issimilarly structured, and operations explained below with respect to aparticular memory cell should be understood to be applicable tocorresponding elements of other memory cells as well.

One memory cell consists of a pair of MOS transistors Qn00, Qn00B and apair of ferroelectric capacitors Cs00, Cs00B. The drain of transistorQn00 is connected to bit line BL0, its source is connected to cell plateelectrode CP0 through ferroelectric capacitor Cs00, and its gate isconnected to word line WL0. The drain of MOS transistor Qn00B isconnected to bit line/BL0, its source is connected to cell plateelectrode CP0 through ferroelectric capacitor Cs00B, and its gate isconnected to word line WL0.

The drain of limiting MOS transistor Qnt0 is connected to bit line BL0,its source is connected to signal line LVcc, which is driven by supplyvoltage Vcc through limiting capacitor Ct0, and its gate is connected tosignal line LCBC, which supplies control signal CBC to limiting MOStransistors Qnt0, Qnt1

Limiting capacitor Ct0 is not connected to bit line BL0 until the numberof readouts already executed reaches a predetermined limiting number nof readouts to be permitted. As shown in FIG. 1, limiting capacitor Ct0and limiting MOS transistor Qnt0 are serially connected, and these areparallelly connected to adjusting capacitor Cb00. The capacitances ofadjusting capacitors Cb00, Cb00B are set to be nearly equal, so whenlimiting MOS transistor Qnt0 is turned on, the capacitance of bit lineBL0 is increased by the capacitance of limiting capacitor Ct0 andbecomes larger than the capacitance of bit line BL0.

Adjusting capacitor Cb00 is connected between bit line BL0 and signalline LVcc, and adjusting capacitor Cb00B is connected between bitline/BL0 and signal line LVcc. These adjusting capacitors Cb00, Cb00Bare provided in order to obtain a larger data readout potentialdifference that can be precisely amplified by sense amplifier SA0.

Bit lines BLO, /BL0 are equalized and precharged by applying controlsignal EQ. In this example, the precharge potential is assumed to beground potential. The gates of controlling MOS transistors Qne0, Qne2,Qne2B are connected to signal line LEQ, with the drain of controllingMOS transistor Qne0 connected to bit line BL0, and its source connectedto bit line /BL0. The drains of controlling MOS transistors Qne2, Qne2Bare connected to bit lines BL0, /BL0 respectively, and the sources areconnected to signal line LVss, which is set at ground potential Vss. Bitlines BL0, /BL0 are also connected to sense amplifier SAO.

Sense amplifier SA0 is connected to signal line LSAE, and is controlledby sense amplifier control signal SAE. A judging circuit 3 fordetermining the number of readouts already executed is connected tosignal line LCBC. A nonvolatile memory device 4 for memorizing thelimiting number of readouts is connected to judging circuit 3, and asubtraction circuit 5 for subtracting the number of readouts alreadyexecuted from the limiting number of readouts is connected tononvolatile memory device 4.

Data readout from ferroelectric capacitors Cs00, Cs00B of thesemiconductor memory device described above will now be explained withreference to FIGS. 2 and 3.

A normally executed readout, occuring while the number of readoutsalready executed is less than the limiting number n of readouts, will beexplained with reference to a particular memory cell of FIG. 1. As shownin FIG. 2, initially, bit lines BLO, /BL0 are grounded, with bit linesBL0, /BL0, word line WL0, cell plate electrode CP0, and signal line LSAEset at logical voltage "L" (low voltage), and signal line LEQ set atlogical voltage "H" (high voltage). By shifting signal line LEQ to "L",controlling MOS transistors Qne0, Qne2, Qne2B are turned off and bitlines BL0, /BL0 are set in a floating state. Word line WL0 and cellplate electrode CP0 are then shifted to "H" applying an electric fieldto ferroelectric capacitors Cs00, Cs00B and enabling data to be read outonto bit lines BL0, /BL0.

The readout operation may be explained in greater detail by referring tothe hysteresis curve of FIG. 3. When data value stored in a memory cellis "1" the states of ferroelectric capacitors Cs00, Cs00B arerespectively at points B and E, reflecting the residual polarization.Conversely, when the data value stored in memory cell is "0", the statesof ferroelectric capacitors Cs00, Cs00B are reversed: Cs00 is at point Eand Cs00B is at point B.

The slopes of straight lines LH1, LL1 in FIG. 3 reflect the bit linecapacitance, and are further determined by shifting point B and point Ehorizontally, in the amount of the magnitude of the electric fieldproduced when word line WL0 and cell plate electrode CP0 are set at "H".

When the readout data is "1", the data stored in ferroelectric capacitorCs00 are read out onto bit line BL0, and its state shifts from point Bto point F, the intersection of straight line LH1 and the hysteresiscurve from point B to point D, representing the change in electricalcharge when an electric field is applied to ferroelectric capacitorCs00.

At the same time, the data stored in ferroelectric capacitor Cs00B areread out onto bit line /BL0, and its state shifts from point E to pointH, the intersection of straight line LL1 and the hysteresis curve frompoint E to point D, representing the change in electrical charge when anelectric field is applied to ferroelectric capacitor Cs00B. Thepotential difference read out between bit lines BL0, /BL0 is Vr1, whichis represented in FIG. 3 as the electric field difference between pointF and point H. The absolute value of the readout potential difference isVr1 whether the stored data is "0" or "1", as the states of bit linesBL0, /BL0 are simply reversed.

When signal line LSAE is shifted to "H", sense amplifier SA0 amplifiesthe potential difference read onto bit lines BL0, /BLO. Consequently,the state of bit line BL0 shifts from point F to point B', and the stateof bit line/BL0 shifts from point H to point D.

Cell plate electrode CP0 is then set at "L" in order to enable datarewriting. This shifts the state of bit line BL0 from point B' to pointA, and the state of bit line/BL0 from point D to point E. Word line WL0and signal line LSAE are then set at "L" and signal line LEQ is set at"H". Bit lines BL0, /BL0 are thus equalized and at a voltage level "L"returning the circuit to its initial condition.

To ensure that the potential difference Vr1 can be amplified exactly bysense amplifier SA0, the bit line capacitances, which determines theslopes of straight lines LH1, LL1, must be precisely set. Bit linecapacitance is a sum of the parasitic capacitance of a bit line BL0,/BL0 and its corresponding adjusting capacitors Cb00, Cb00B. Bit linesBL0, /BL0 have nearly equal capacitance, and the total bit linecapacitance can be adjusted by adjusting capacitors Cb00 and Cb00B.

The above discussion concerns only the operation of reading out storeddata. Now, a method of limiting the number of readouts according to thepresent invention will be explained.

First, a limiting number of readouts, n, is memorized in nonvolatilememory device 4, and subtraction circuit 5 reduces n by one with eachreadout executed.

As long as the number of readout operations already executed does notexceed n, judging circuit 3 supplies a logical voltage "L" continuouslyto the gate of limiting MOS transistor Qnt0, preventing limitingcapacitor Ct0 from adding to the bit line capacitance. During thisstage, readouts can be executed normally and the potential differenceVr1 will remain steady, as indicated in FIG. 3.

On the (n+1)th attempted readout, where n is the limiting number ofreadouts, judging circuit 3 outputs a logical voltage "H", turning onlimiting MOS transistor Qnt0 This connects limiting capacitor Ct0 inparallel to adjusting capacitor Cb00, adding to the bit line capacitanceand rotating straight line LH1 to straight line LH2.

Thus, in reading out a data value "1", the readout potential differenceis expressed by a potential difference -Vr2 between points G and H,where point G is the intersection of straight line LH2 and thehysteresis curve from point B to D. Since the potential difference -Vr2is of an opposite polarity from the potential difference of the datanormally read out, Vr1, reading and writing operations of data value "0"are performed instead, overwriting and destroying the stored data.

Similarly, the potential difference obtained by reading out a data valueof "0" on the (n+1)th attempted read is expressed by Vr3, the potentialdifference between the point F and point I.

As described above, this first embodiment of the present inventionlimits the number of readouts available to a data user by essentiallyclearing the stored data on the (n+1)th read, and reading and rewritingall data values as "0". Thus, by the (n+2)th attempted readout, eachdata value "1" has been destroyed by being rewritten as "0", so all datastored in the memory cell are "0"s. Therefore, the readout potentialdifference will be either Vr1 or Vr3, regardless of whether the outputof judging circuit 3 indicates that the limiting number of readouts hasbeen reached.

It should be understood that the above example in which limitingcapacitor Ct0 is disposed in parallel to adjusting capacitor Cb00 isjust one arrangement of the first embodiment of the present invention.Alternatively, limiting capacitor Ct0 could be disposed in parallel toadjusting capacitor Cb00B instead, in which case data value "0" would bedestroyed.

Another possible variation of the above example is to replacesubtraction circuit 5 with a counter for counting the number ofreadouts.

Embodiment 2

FIG. 4 shows a second embodiment of the present invention, modifying thefirst embodiment shown in FIG. 1 only in that limiting MOS transistorsQnt0B, Qnt1B and limiting capacitors Ct0B, Ct1B are disposed in parallelto adjusting capacitors Cb01B, Cb11B rather than adjusting capacitorsCb01, Cb11. In order to maintain bit line capacitances of BL0 and /BL0to be approximately equal, limiting capacitors Ct0B, Ct1B and adjustingcapacitors Cb01B, Cb11B are set at a capacitance such that their sum isnearly equal to the capacitance of adjusting capacitors Cb01, Cb11.

The readout operation of this embodiment will now be explained withreference to ferroelectric capacitors Cs00 and Cs00B. In contrast to thefirst embodiment of the present invention, judging circuit 3 outputslogical voltage "H" while the number of readouts already executed isless than the limiting number of readouts, n, turning on limiting MOStransistor Qnt0B. Thus, the bit line capacitances of bit lines BL0, /BL0are approximately equal, and normal readouts are conducted as shown inthe timing chart of FIG. 5 and the potential difference between point Fand point H, Vr1, is read as data.

When the number of readouts already executed reaches the limiting numberof readouts, n, judging circuit 3 outputs logical voltage "L", turningoff limiting MOS transistor Qnt0B and cutting off limiting capacitorCt0B from bit line /BL0. This decreases the bit line capacitance of bitline /BL0 and is reflected in FIG. 6 in a less steep slope of straightlines LH1 or LL1.

At this point, if attempting to read a data value "1", straight line LL1rotates to straight line LL3 and the readout potential difference isexpressed by the potential difference -Vr4 between points F and K, wherepoint K is the intersection point between straight line LL3 and thehysteresis curve. As indicated, potential difference -Vr4 is of apolarity opposite to that of the stored data as it would have beennormally read out, so although the data value stored was "1", In otherwords, data value "0" is both read and rewritten, resulting in theoverwriting of the originally stored data.

If reading a data value "0", straight line LH1 rotates to straight lineLH3 and the readout potential difference is expressed by the potentialdifference -Vr5 between points H and J, where point J is theintersection between straight line LH3 and the hysteresis curve. Thus,data value "0" is both read and rewritten, accurately reflecting thestored data value.

Like the first embodiment of the present invention, this secondembodiment limits the number of readouts available to a data user byreading and rewriting all stored data as "0"s on the (n+1)th attemptedreadout. Hence, by the (n+2)th attempted readout, all stored data havingvalue "1" will have been destroyed and all of the memory cell data willbe "0"s. The readout potential difference will be either Vr1 or Vr3regardless of whether the output from judging circuit 3 indicates thatthe limiting number n of readouts permitted has been reached.

As a variation of this second embodiment of the present invention,limiting capacitor Ct0B, limiting MOS transistor Qnt0B, adjustingcapacitor Cb01B may be connected to bit line BL0, and adjustingcapacitor Cb01 may be connected to bit line /BL0. In this case, oppositefrom the above example, data value "0" rather than data value "1" isdestroyed.

Embodiment 3

A schematic circuit diagram of a third embodiment of the presentinvention is shown in FIG. 7, another modification of the firstembodiment shown in FIG. 1. The difference in the third embodiment fromthe first embodiment is the addition of limiting capacitors Ct0B, Ct1Bare connected to bit lines /BL0, /BL1 through limiting MOS transistorsQnt0B, Qnt1B, disposed in parallel to adjusting capacitors Cb00B, Cb10B.

The capacitances of limiting capacitors Ct0B, Ct1B are set to be nearlyequal to the capacitance of limiting capacitors Ct0, Ct1.

The readout operation of the semiconductor memory device of the thirdembodiment of the present invention is now explained with respect toferroelectric capacitors Cs00, Cs00B.

The readout timing of this embodiment of the present invention isidentical to that of the first embodiment shown in FIG. 2. As long asthe number of readouts already executed is less than the limiting numberof readouts, n, judging circuit 3 outputs a logical voltage "L", turningoff limiting MOS transistors Qnt0, Qnt0B.

During this normal readout period, limiting MOS transistors Ct0, Ct0Bare off, so limiting capacitors Ct0, Ct0B are not connected to adjustingcapacitors Cb00 and Cb00B. Thus, the potential difference Vr1, thedifference between point F and point H as shown in FIG. 8, is normallyread out as in the first embodiment.

When the number of readouts already executed reaches the limitingnumber, n, of readouts, judging circuit 3 outputs logical voltage "H",turning on limiting MOS transistors Qnt0, Qnt0B. Thus, both limitingcapacitors Ct0, Ct0B are connected to adjusting capacitors Cb00, Cb00Bin parallel, increasing the bit line capacitance of bit lines BL0, /BL0.Thus, straight line LH1 is rotated to straight line LH4, straight lineLLI is shifted to straight line LL4, and the potential differencebetween points M and N, Vr6, is read out.

As shown in FIG. 8, the magnitude of potential difference -Vr6 is sosmall that its normal amplification by sense amplifier SA0 isimpossible. Thus, this third embodiment of the present inventionprevents readouts after the nth readout by making the data impossible toread.

Embodiment 4

The basic circuit construction of the fourth embodiment of the presentinvention is identical to that of the third embodiment shown in FIG. 7.However, when limiting MOS transistors Qnt0, Qnt0B, Qnt1, Qnt1B areturned on, the capacitances of limiting capacitors Ct0, Ct0B, Ct1, Ct1Band adjusting capacitors Cb00, Cb00B, Cb10, Cb10B are set such that thetotal bit line capacitances will result in straight lines LH1, LL1having slopes as indicated in FIG. 8.

In contrast to the third embodiment, judging circuit 3 outputs logicalvoltage "H" during normal readouts, turning on limiting transistorsQnt0, Qnt0B. Thus, limiting capacitors Ct0, Ct0B are normally connectedto adjusting capacitors Cb00, Cb00B in parallel, and potentialdifference Vr1 as shown in FIG. 9 is normally read out.

When the number of readout operations already executed reaches thelimiting number of readout operations, n, judging circuit 3 outputslogical voltage "L", turning off limiting MOS transistors Qnt0, Qnt0Band disconnecting limiting capacitors Ct0, Ct0B from bit lines BL0,/BL0. This decrease in bit line capacitance rotates straight line LH1 tostraight line LH5, and straight line LL1 to straight line LL5, and thepotential difference between point P and point Q, Vr7, is read out. Asshown in FIG. 9, however, the magnitude of potential difference Vr7 isvery small and cannot be normally amplified by sense amplifier SA0.Thus, as in the third embodiment of the present invention discussedabove, the fourth embodiment limits the number of possible readouts bymaking the stored data impossible to read after the nth readout.

Embodiment 5

The fifth embodiment of the present invention as shown in FIG. 10 isidentical to the first embodiment shown in FIG. 1, except that limitingcapacitors Ct0, Ct1, limiting MOS transistors Qnt0, Qnt1, signal lineLCBC, judging circuit 3, nonvolatile memory device 4, and subtractioncircuit 5 are all eliminated from the circuit.

In other words, the circuit construction of this embodiment is identicalto that of the first embodiment with limiting MOS transistors Qnt0, Qnt1permanently turned off. Thus, the operation timing is identical with theoperation timing of the first embodiment of the present invention shownin FIG. 2.

The present invention permits normal readout only while the number ofreadouts already executed is less than the limiting number n of readoutspermitted. FIG. 11 is a timing chart showing the last permitted readout(identical to the operation shown in FIG. 2) along with the datarewriting operation conducted within the semiconductor memory device ofthe present invention.

A normal readout operation as shown in FIG. 2 concludes with a rewritingof the data conducted by shifting the logical voltages of word line WL0and cell plate electrode CP0 from "H" to "L" before shifting signal lineLEQ from "L" to "H".

However, when a rewriting operation according to FIG. 11 is attemptedafter the nth normal data readout operation, signal line LSAE is changedfrom "H" to "L" and signal line LEQ is changed from "L" to "H", prior toword line WL0 and cell plate electrode CP0 being shifted from "H" to"L". This order equalizes the bit lines BL0, /BL0 at voltage level "L",setting the data values held to "0" rather than enabling an accuraterewrite.

These differences between the timing of the reversing of logical voltageduring normal rewriting operations and rewriting operations attemptedafter the nth normal readout operation are performed by using a signalreversing circuit (not shown in FIG. 10).

By these signal changes, the state on the hysteresis curve of a memorycell storing data value "1" is sequentially shifted from point B topoint E taking a path of 1-2-3-4(B-F-B'-D-H-E), as shown in FIG. 12. Ifthe memory cell is storing a data value "0", its state is sequentiallyshifted from point E back to point E, taking a path of1'-2'-3'-4'(E-D-H-E).

In other words, by altering the timing of the readout and rewriteoperations, data in the memory cells are all erased by equalizing theferroelectric capacitors Cs00, Cs00B to a "0" state. Thus, accurate datareadout becomes impossible after the nth readout.

As always, variations of the above embodiment of the present inventionare available. For example, one possible variation could be to changethe operation timing by means of a control circuit consisting of judgingcircuit 3, nonvolatile memory device 4, and subtraction circuit 5 asshown in FIG. 1.

Embodiment 6

The sixth embodiment of the present invention, shown in FIG. 13, is amodification of the fifth embodiment, shown in FIG. 10, with thedifferences being the additions of data lines DL, /DL and signal linesLBS0, LBS1 for supplying bit line selection signals BS0, BS1.

Data lines DL, /DL are respectively connected to bit lines BL0, BL1,/BL0, /BL1 through MOS transistors Qnd0, Qnd1, Qnd0B, Qnd1B. Gates ofMOS transistors Qnd0, Qnd0B are connected to signal line LBS0, and gatesof transistors Qnd1, Qnd1B are connected to signal line LBS1.

The normal data readout operation in the sixth embodiment is identicalto that in the fifth embodiment as indicated in FIG. 2. However, asshown in FIG. 14, the rewriting operation after the nth readoutoperation differs.

As shown in FIG. 14, after completing the readout operations, thelogical voltage of signal line LSAE is changed from "H" to "L" and "H"is written into ferroelectric capacitors Cs00, Cs00B, Cs10, Cs10Bthrough data lines DL, /DL, since MOS transistors Qnd0, Qnd0B, Qnd1,Qnd1B are turned on. After this has been completed, cell plate electrodeCP0 and word line WL0 are changed from "H" to "L".

If a data value "1" is stored in a ferroelectric capacitor, the state issequentially shifted from point B back to point B over the path of1-2-5-6-7(B-F-B'-A-B), as shown in FIG. 15. On the other hand, if datavalue "0" is stored, the state is sequentially shifted from point E topoint B over the path of 1'-2'-5'-6'-7' (E-H-D-H-E-A-B). Thus, datavalue "1" is written in all ferroelectric capacitors, overwriting theactual data in the memory cells such that the data cannot be accuratelyread out after the nth readout operation.

A possible variation of the data destruction method described above isto write an "L" rather than an "H" into each ferroelectric capacitor.The timing chart of this operation is shown in FIG. 16 and thehysteresis curve is shown in FIG. 17.

As shown in FIG. 16, after finishing the data readout operation, thelogical state of signal line LSAE is changed from "H" to "L", and after"L" is written in each ferroelectric capacitor through data lines DL,/DL, cell plate electrode CP0 and word line WL0 are changed from "H" to"L".

If a data value "1" is stored in a memory cell, the state issequentially shifted from point B to point E over the path of 1-2-8-9-(B-F-B'-D-E) as shown in FIG. 17. If a data value "0" is stored, thestate is sequentially shifted from point E back to point E over a pathof 1''2'-8'-9' (E-H-D-H -E). Thus, data value "0" is written in eachferroelectric capacitor, overwriting the actual data stored.

Embodiment 7

The seventh embodiment of the present invention shown in FIG. 18 is amodification of the sixth embodiment shown in FIG. 13, with thedifference being the addition of reversing circuit 6 between data linesDL, /DL.

The normal data readout operation in this embodiment is identical tothat in the sixth embodiment and is represented in FIG. 2. However, therewriting operation after the nth readout operation differs. FIG. 19 isa timing chart of the nth readout operation and the subsequent datarewriting operation.

As shown in FIG. 19, after completing the readout operation, the logicalvoltage of signal line LSAE is shifted from "H" to "L". Then, thereversing circuit 6 reverses the logical voltages on data lines DL, /DL,rewriting the reversed data into the memory cells. After the reversaland rewriting are completed, the logical voltage of cell plate electrodeCP0 and word line WL0 shift from "H" to "L".

If a data value "1" is stored in the ferroelectric capacitor, the stateis sequentially shifted from point B to point E over the path of1-2-10-11-12(B-F-B'-D-E), as shown in FIG. 20. If the data value storedis a "038 the state is sequentially shifted from point E to point B overthe path of 1'-2'-10'-11'-12'-(E-H-D-H-E-A-B).

This operation by the reversing circuit 6 destroys all the data storedin the memory cells by reversing all data values of "0" or "1" stored,making subsequent accurate readout operations impossible.

Embodiment 8

The eighth embodiment of the invention is another variation of the fifthembodiment shown in FIG. 10, with the difference that the capacitancesof adjusting capacitors Cb00, Cb00B of the eighth embodiment are largerthan those in the fifth embodiment. Thus, the slopes of straight linesLH6 and LL6, shown in FIG. 22, are steeper than those of the straightlines LH1 and LL1 shown in FIG. 12.

The normal data readout operation is identical to that performed in thefifth embodiment, and is represented in FIG. 2. However, the rewritingoperation after the nth readout differs. FIG. 21 shows the nth readoutand the subsequent data rewriting operation, and FIG. 22 represents ahysteresis curve corresponding to the readout and rewrite operation.

After the nth readout, the potential difference between point R andpoint T Vr8 is read out. In the subsequent data rewriting operation madeafter the nth readout operation, as shown by FIG. 21, the logicalvoltage of cell plate electrode CP0 is changed from "H" to "L" after thelogical voltage of word line WL0 is changed from "H" to "L" turning offMOS transistors Qn00, Qn00B, making it impossible to rewrite.

This, if a data value "1" is stored, the state is sequentially shiftedfrom point B to point B" over the path of 13-14-15-16 (B-R-B"). If thedata value stored is a "0", the state is sequentially shifted from pointE back to point E over the path of 13'-14'-15'-16'(E-T-D-T-E).

The operation of a ferroelectric capacitor storing a data value "1" isaltered by this rewrite. Recalling that the straight lines in thehysteresis curve are defined not only by their slopes but also by theresidual charges remaining in the ferroelectric capacitors after thepower supply has been cut off, straight line LH6 is shifted downwards toLH7 when the state ferroelectric capacitor shifts from point B to pointB". Consequently, when the (n+1)th readout operation is attempted,straight line LH6 has been shifted to straight line LH7, and thepotential difference read out is Vr9 rather than Vr8.

The magnitude of potential difference Vr9 is so small that it cannot beamplified by the sense amplifier SA0. Thus, this eighth embodiment ofthe present invention limits the number of readouts by decreasing thepotential difference to the extent that readout becomes impossible.

Embodiment 9

The circuit construction of the ninth embodiment is similar to that ofthe fifth embodiment shown in FIG. 10 except that the capacitances ofadjusting capacitors Cb00 and Cb00B are smaller than those in the fifthembodiment. This decreased capacitance makes the slopes of the straightlines less steep, and is reflected in straight lines LHA1 and LLA1 shownin FIG. 24, whose slopes have a lesser absolute value than those ofstraight lines LH1 and LL1 shown in FIG. 12.

Although the normal data readout operation is the same as that of thefifth embodiment (represented in FIG. 2), the rewriting operationperformed after the nth readout operation differs. FIG. 23 shows readoutoperation made after the nth readout, and the data rewriting operation;FIG. 24 shows the corresponding hysteresis curve.

At the nth readout operation, the potential difference between point U1and point V, VrA1, is read out. During the rewriting operation followingthe nth readout operation, the logical voltage of cell plate electrodeCP0 is changed from "H" to "L" after the logical voltage of word lineWL0 is changed from "H" to "L" as shown by FIG. 23 The state of aferroelectric capacitor storing a data value "1" is thereforesequentially shifted from point B to point B1, over the path21-22-23-24(B-U1-B1) as shown in FIG. 24. If the ferroelectric capacitoris storing a data value "0", the state is sequentially shifted frompoint E back to point E, over the path 21'-22'-23'-24' (E-V-D-V-E).

When attempting to perform the (n+1)th readout, the potential differencebetween point U2 and point V, VrA2, is read out, and point B1 is shiftedto point B2.

By repeating the above readout and rewriting operations, point B1 issequentially shifted to point B2, then point B3, eventually arriving atpoint Bm after the mth rewriting operation, giving readout potentialdifference VrAm.

When potential difference VrAm decreases to a voltage level too small tobe amplified by sense amplifier SA0, subsequent readout operations willbe impossible. The maximum number of possible readout operations in thisembodiment is therefore not limited by n, the predetermined limitingnumber of readouts to be permitted, but rather by m, which can beadjusted by setting adjusting capacitors Cb00, Cb00B at a propercapacitance. Thus, this embodiment is effective when the limiting numberof readouts cannot be initially determined.

Embodiment 10

The tenth embodiment of the present invention shown in FIG. 25 is amodification of the fifth embodiment shown in FIG. 10. The difference inthis embodiment is the addition of a control circuit controlling thecell plate electrodes CP0, CP1 and sense amplifiers SA0, SA1.

The control circuit consists of determining MOS transistors Qnf0, Qnf1,Qnf2 for determining the connection of a control signal SRC to thememory cell region, a reversing circuit 7 for reversing control signalSRC, cell plate electrodes CP0, CP1, and grounding MOS transistors Qng0,Qng1, Qng2 for grounding cell plate electrodes CP0, CP1 and senseamplifiers SA0, SA1.

Signal line LSRC is connected to the gates of determining MOStransistors Qnf0, Qnf1, Qnf2, and the signal line L/SRC is connected tothe gates of grounding MOS transistors Qng0, Qng1, Qng2. As long as thenumber of data readout operations already executed is less than thepredetermined limiting number, n, of readouts, the timing of theoperation is fundamentally the same as that in the fifth embodiment ofthe present invention. Namely, since the control signal SRC supplied tothe gates of determining MOS transistors Qnf0, Qnf1, Qnf2 and thesignal/SRC supplied to the gates of grounding MOS transistors Qng0,Qng1, Qng2 are inversely related, grounding MOS transistors Qng0, Qng1,Qng2 are off when determining MOS transistors Qnf0, Qnf1, Qnf2 are on.

FIG. 25 additionally shows that reversing circuit 7 is inserted betweensignal lines LSRC, L/SRC, and that judging circuit 3, nonvolatile memorydevice 4, and subtraction circuit 5 are serially connected to signalline LSRC.

Once the number of readouts executed reaches the predetermined limitingnumber n, which is memorized in nonvolatile memory device 4, judgingcircuit 3 outputs control signal SRC to turn off determining MOStransistors Qnf0, Qnf1, Qnf2 and to turn on grounding MOS transistorsQng0, Qng1, Qng2. This stops the control signal from reaching cell plateelectrodes CP0, CP1 and grounds signal line LSAE, making the readoutfrom and the writing into the memory cells impossible.

Thus, this embodiment of the present invention limits the number ofreadouts available to a data user by preventing movement of any chargestored in ferroelectric capacitors Cs00, Cs00B, Cs01, Cs01B, Cs10,Cs10B, Cs11, Cs11B after the nth readout, thereby locking the originaldata therein.

Embodiment 11

The eleventh embodiment of the present invention shown in FIG. 26 is amodification of the tenth embodiment shown in FIG. 25. The onlydifference is the substitution of a control circuit for controlling wordlines WL0, WL1 and cell plate electrodes CP0, CP1, replacing the controlcircuit of the tenth embodiment controlling cell plate electrodes CP0,CP1 and sense amplifiers SA0, SA1.

Word lines WL0, WL1 are connected to signal line LSRC throughdetermining MOS transistors Qnh0, Qnh1, and are further connected tosignal line L/SRC through grounding MOS transistors Qni0 and Qni1. Thus,the normal data readout operation is essentially identical to that ofthe tenth embodiment of the present invention.

Specifically, since the signals supplied to the gates of determining MOStransistors Qnf0, Qnf1, Qnh0, Qnh1, and the signals supplied to thegates of grounding MOS transistors Qng0, Qng1, Qni0, Qni1 are inverselyrelated, grounding MOS transistors Qng0, Qng1, Qni0, Qni1 are turned offwhen determining MOS transistors Qnf0, Qnf1, Qnh0, Qnh1 are turned on.Therefore, during normal readout operations, the signals on word linesWL0, WL1 and cell plate electrodes CP0, CP1 are supplied to the memorycell region and the semiconductor memory device continues to be normallyoperated.

When the number of readouts executed reaches the limiting number n ofreadouts permitted, which is memorized by nonvolatile memory device 4,judging circuit 3 outputs control signal SRC turning off determining MOStransistors Qnf0, Qnf1, Qnh0, Qnh1 and turning on grounding MOStransistors Qng0, Qng1, Qni0, Qni1.

Thus, word lines WL0, /WL0 and cell plate electrodes CP0, CP1 aregrounded, making subsequent readout and writing operations impossible.No movement of charges stored in ferroelectric capacitors Cs00, Cs00B,Cs01, Cs01B, Cs10, Cs10B, Cs11, Cs11B can take place and the stored datais locked therein.

Of course, it should be understood that a wide range of changes andmodifications can be made to the preferred embodiments described above.For example, although the above embodiments show memory cells consistingof two MOS transistors and two ferroelectric capacitors, a memory cellof the semiconductor memory device of the present invention mayalternatively comprise one MOS transistor and one ferroelectriccapacitor.

Furthermore, in the control circuit limiting the number of readoutspermitted to a predetermined limit, a counter circuit for counting thenumber of readouts executed may be used instead of the subtractioncircuit described above.

It is therefore intended that the foregoing detailed description beunderstood that it is the following claims, including all equivalents,which are intended to define the scope of this invention.

What is claimed is:
 1. A semiconductor memory device comprising:a pairof bit lines; a word line; a cell plate electrode; a memory cell forstoring normal data, connected to said bit lines, said word line, andsaid cell plate electrode; and a prevention means for preventing readoutof said normal data stored in said memory cell by destroying said normaldata, after a number of readouts already executed on said normal datareaches a predetermined limiting number of readouts.
 2. A semiconductormemory device according to claim 1, wherein said memory cell comprises aMOS transistor and a ferroelectric capacitor.
 3. A semiconductor memorydevice comprising:a pair of bit lines; a word line; a cell plateelectrode; a memory cell for storing data, connected to said bit lines,said word line, and said cell plate electrode; and a prevention meansfor preventing normal readout of said data store in said memory cell,after a number of readouts already executed on said data reaches apredetermined limiting number of readouts, wherein said preventing meanscomprises an alteration means for altering bit line capacitance of atleast one of said bit lines.
 4. A semiconductor memory device accordingto claim 3, wherein said alteration means comprises a switch connectedto a capacitor, wherein said switch is also connected to at least one ofsaid bit lines for preventing readouts on said one or more connected bitlines.
 5. A semiconductor memory device according to claim 4, whereinbit line capacitances of a first of said bit lines is different from bitline capacitance of a second of said bit lines when said switch is on.6. A semiconductor memory device according to claim 4, furthercomprising at least one adjusting capacitor connected to at least one ofsaid bit lines for adjusting bit line capacitance of said one or moreconnected bit lines, wherein said bit lines have approximately equalcapacitance when said switch is on.
 7. A semiconductor memory deviceaccording to claim 4, wherein bit line capacitance of said bit lineswhen said switch is on differs from bit line capacitance of said bitlines when said switch is off.
 8. A semiconductor memory deviceaccording to claim 3, further comprising a control means connected tosaid alteration means for determining whether a number of readoutsalready executed on said stored data has reached said predeterminedlimiting number of readouts.
 9. A semiconductor memory device accordingto claim 8, wherein said control means comprises a subtraction circuitfor subtracting a number of readouts already executed on said storeddata from said predetermined limiting number of readouts, a memory meansfor memorizing said subtracted number, and a judging circuit fordetermining whether said subtracted number has reached saidpredetermined limiting number of readouts.
 10. A semiconductor memorydevice comprising:a pair of bit lines; a word line; a cell plateelectrode; a memory cell for storing data, connected to said bit lines,said word line, and said cell plate electrode; and a prevention meansfor preventing normal readout of said data stored in said memory cell,after a number of readouts already executed on said data reaches apredetermined limiting number of readouts, wherein said prevention meanscomprises a signal reversing means for altering a normal reversingtiming for a rewriting operation of at least one logical voltagesupplied to said memory cell for a rewriting operation conducted aftersaid predetermined limiting number of readouts have been executed.
 11. Asemiconductor memory device according to claim 10, wherein said signalreversing means comprises an equalizing means for equalizing logicalvoltages of said bit lines after said predetermined limiting number ofreadouts have been executed on said stored data.
 12. A semiconductormemory device according to claim 11 wherein said equalizing meanscomprises a reversing means for reversing logical voltage of one of saidbit lines by a control signal precharging said bit lines.
 13. Asemiconductor memory device according to claim 11, further comprising apair of data lines, each respectively connected to one of said bitlines, wherein said equalizing means comprises said data lines,supplying equal logical voltages to both of said bit lines.
 14. Asemiconductor memory device according to claim 10, wherein said signalreversing means comprises a voltage reversing means for reversinglogical voltages of said bit lines and subsequently reversing logicalvoltage of said cell plate electrode.
 15. A semiconductor memory deviceaccording to claim 10, further comprising a control means connected tosaid signal reversing means, wherein said control means determineswhether a number of readouts already executed on said stored data hasreached said predetermined limiting number of readouts.
 16. Asemiconductor memory device according to claim 15, wherein said controlmeans comprises a subtraction circuit for subtracting a number ofreadouts already executed on said stored data from said predeterminedlimiting number of readouts, a memory means for memorizing saidsubtracted number, and a judging circuit for determining whether saidsubtracted number has reached said predetermined limiting number ofreadouts.
 17. A semiconductor memory device comprising:a pair of bitlines; a word line; a cell plate electrode; a memory cell for storingdata, connected to said bit lines, said word line, and said cell plateelectrode; and a prevention meads for preventing normal readout of saiddata stored in said memory cell, after a number of readouts alreadyexecuted on said data reaches a predetermined limiting number ofreadouts, wherein said prevention means is a stopping means for stoppingsupply of a control signal to said memory cell after said predeterminedlimiting number of readouts have been executed on said stored data. 18.A semiconductor memory device according to claim 17, further comprising:a sense amplifier connected to said bit lines, wherein said stoppingmeans comprises a switch connected to said cell plate electrode and tosaid sense amplifier; and a grounding means for grounding each of saidcell plate electrode and said sense amplifier through said switch.
 19. Asemiconductor memory device according to claim 17, wherein said stoppingmeans comprises a switch connected to said word line and to said cellplate electrode, and a grounding means for grounding said word line andsaid cell plate electrode through said switch.
 20. A semiconductormemory device according to claim 17, further comprising a control meansconnected to said stopping means, wherein said control means determineswhether a number of readouts already executed on said stored data hasreached said predetermined limiting number of readouts.
 21. Asemiconductor memory device according to claim 20, wherein said controlmeans comprises a subtraction circuit for subtracting a number ofreadouts already executed on said stored data from said predeterminedlimiting number of readouts, a memory means for memorizing saidsubtracted number, and a judging circuit for determining whether saidsubtracted number has reached said predetermined limiting number ofreadouts.
 22. A method of limiting a number of readouts of normal datastored in a semiconductor memory device comprised of a pair of bitlines, a word line, a cell plate electrode, a memory cell connected tosaid bit lines, said word line, and said cell plate electrode, whereinsaid limiting method comprises the steps of:determining a number ofreadouts already executed on said normal data; determining whether saidnumber of readouts already executed on said normal data has reached apredetermined limiting number of readouts; preventing subsequentreadouts of said normal data by destroying said normal data upondetermination that said number of readouts already executed on saidnormal data has reached said predetermined limiting number of readouts.23. A method according to claim 22, wherein said memory cell iscomprised of a MOS transistor and a ferroelectric capacitor.
 24. Amethod according to claim 22, wherein said step of determining whethersaid number of readouts already executed on said normal data has reachedsaid predetermined limiting number of readouts is achieved by a controlmeans.
 25. A method of limiting a number or readouts of data stored in asemiconductor memory device comprised of a pair of bit lines, a wordline, a cell plate electrode, a memory cell connected to said bit lines,said word line, and said cell plate electrode, wherein said limitingmethod comprises the steps of:determine a number of readouts alreadyexecuted on said stored data; determining whether said number ofreadouts already executed on said stored data has reached apredetermined limiting number of readouts; preventing subsequentreadouts of said stored data upon determination that said number ofreadouts already executed on said stored data has reached saidpredetermined limiting number of readouts, wherein said step ofdetermining whether said number of readouts already executed on saidstored data has reached said predetermined limiting number of readoutsis achieved by a control means comprising:a subtracted circuit forsubtracting a number of readouts already executed on said stored datafrom said predetermined limiting number of readouts; a memory means formemorizing said subtracted number; and a judging circuit for determinewhether said subtracted number has reached said predetermined limitingnumber of readouts.
 26. A method of limiting a number of readouts ofdata stored in a semiconductor memory device comprised of a pair of bitlines, a word line, a cell plate electrode, a memory cell connected tosaid bit lines, said word line, and said cell plate electrode, whereinsaid limiting method comprises the steps of:determining a number ofreadouts already executed on said stored data; determining whether saidnumber of readouts already executed on said stored data has reached apredetermined limiting number of readouts; preventing subsequentreadouts of said stored data upon determination that said number ofreadouts already executed on said stored data has reached saidpredetermined limiting number of readouts, by altering bit linecapacitance of at least one of said bit lines.
 27. A method according toclaim 26, wherein said semiconductor memory device further comprises atleast one adjusting capacitor connected by a switch to at least of oneof said bit lines, and said preventing step is achieved by adjustingsaid bit line capacitance of at least one of said bit lines by turningon said switch, connecting said adjusting capacitor to said connectedbit line.
 28. A method of limiting a number of readouts of data storedin a semiconductor memory device comprised of a pair of bit lines, aword line, a cell plate electrode, a memory cell connected to said bitlines, said word line, and said cell plate electrode, wherein saidlimiting method comprises the steps of:determining a number of readoutsalready executed on said stored data; determining whether said number ofreadouts already executed on said stored data has reached apredetermined limiting number of readouts; preventing subsequentreadouts of said stored data upon determination that said number ofreadouts already executed on said stored data has reached saidpredetermined limiting number of readouts, by equalizing logical voltageof said bit lines.